A single edge triggered flip-flop which is able to store a one bit. Mostly it is a part of computational circuits or used as registers in the pipeline structure to store the data for the further pro- cessing. Flip-Flops are used as a main part of the digital synchronous circuit. Cutting the frequency of the clock by half the power is re- duced by the half on the clock distribution network. The power of the clocking system is given by the sum of the power consumed by the clock dis- tribution network and the power consumed by the flip-flops. Dual edge clocking can be used to save half of the power on the clock distribution network. Thus, the power can be reduced by decreasing the clock frequency. Capacitances are affected by the characteristics of the devices. But decreasing the supply voltage beyond the certain limit will result in ex- ponential increase in the leakage current.
From the equation 1 it is clear that decreasing the supply voltage has a quadratic effect on decreasing the power dissipation P.
P=αfCV 2 (1) Where α is the switching activity, f is the frequency and C is the capacitance and V is the supply voltage. The switching power is given by formula given in equation 1. In the digital circuits, the power dissipation on the signal switching (dynamic) is dominant. There are basically four sources of power dissipation digital CMOS circuits which is the switch- ing power, short circuit power, leakage power and the static power. From this clock distribution power 90% is consumed by last part of the clock distribution network. this much power is dissipated by the clock distribution circuit out of total chip power. Clock related power consumption is 30-60% of the total chip power i.e. Flip-flops are the critical timing elements which has a large impact on the circuit speed and power dissipation of the system. Higher clock speeds, increased levels of integration and tech- nology scaling are causing unabated increases in power con- sumption. As VLSI cir- cuits continue to grow and technologies evolve, the level of integration is increased and higher clock speeds are achieved. CMOS has been the dominant technology for very large scale integration (VLSI) implementations.
As more transistors are integrated with each new technology, leakage energy is also going to dominate the dynamic power consumption.
#EDGE TRIGGERED FLIP FLOP CIRCUIT DIAGRAM PORTABLE#
Consumer desire has caused a demand for ever increasing the number of portable applications requiring low power and high throughput. Normally the high performance chips have high integration density and high clock frequency, which tend to dictate power consumption. - WITH the widespread use of the mobile devices in modern society, power efficiency and energy savings becomes the crit- ical issues for designers.
Index Terms - Dual Edge Triggered Flip-Flop, Conditional Discharge, Conditional Prechrage, CMOS design, Explicit Pulsed, Sense The delay factor is improved by the factor of the 26.5% as compared to the existing design of the flip-flop. Comparing with the previous work of the dual edge triggered flip-flops, the proposed one saved power upto 20.7%. Simulation using TSPICE and a 0.18µm CMOS technology shows that the proposed design has low power dissipation and small delay as compared to the existing design which use a conditional precharge technique in the design for removing the redundant transitions. By using the fast improved version of the nickolic latch along with the sense amplifier approach for the latching and the sensing stage the delay factor of the circuit is improved. The redundant transitions are eliminated by using the conditional technique named conditional discharge technique. Low Power Explicit Pulsed Conditional DischargeĪbstract - An explicit pulsed double edge triggered sense amplifier flip-flop for the low power and low delay is presented in this paper. International Journal of Scientific & Engineering Research, Volume 3, Issue 11, November-2012 1 Low Power Explicit Pulsed Conditional Discharge Double Edge Triggered Flip-Flop